This invention relates to digital delay circuits. More particularly, this invention relates to high resolution digital delay circuits for phase-locked loops (PLLs) and delay-locked loops (DLLs).
PLLs and DLLs are widely used in many applications. Typically, PLLs and DLLs output one or more clock signals locked to both the phase and frequency of a reference clock. PLLs and DLLs lock the output clock to the reference clock by adjusting the time delay of an associated delay circuit. PLLs and DLLs may be used in dynamic random access memory (DRAM) applications to, for example, synchronize DRAM reads, writes and refreshes to a reference clock.
Conventional analog PLLs and DLLs use a plurality of analog voltage-controlled delay elements (VCDs) to lock the output clock to the reference clock. The time delays generated by the VCDs are adjustable and can be controlled by adjusting a control voltage. It is well known that analog designs are more difficult to mass produce reliably with stated specifications and are less portable to various process technologies than digital designs.
Conventional digital PLLs and DLLs use a plurality of serially-connected digital delay elements to lock the output clock to the reference clock. While the time delays of the digital delay elements are adjustable, in present art all of the delay elements are controlled simultaneously by the same digital control signal. In other words, the time delay of one delay element in the serially-connected chain cannot be adjusted without simultaneously adjusting the time delays of all other delay elements in the chain. This causes conventional digital delay circuits to have low resolution.
In general, higher resolution delay circuits (i.e., delay circuits that provide smaller minimum delay adjustments) allow associated PLLs and DLLs to more accurately lock the output clock to the reference clock. Higher resolution delay circuits also allow the associated PLLs and DLLs to more accurately maintain the locked condition in response to process, voltage and temperature (PVT) variations.
In view of the foregoing, it would be desirable to provide high resolution digital delay circuits.